library ieee;
use ieee.std_logic_1164.all;

entity loconet_protocol is
  port (
    clk         : in  std_logic;
    reset       : in  std_logic;
    byte_entry  : in  std_logic_vector(7 downto 0);
    byte_ready  : in  std_logic;
    LocoID      : out std_logic_vector(7 downto 0);
    SensorID    : out std_logic_vector(7 downto 0);
    SensorEvent : out std_logic);
end loconet_protocol;


architecture synth of loconet_protocol is
  type state_type is (READ_COP, READ_LONG, READ_RESERVED, READ_RESERVED_2, READ_RECEPTOR,
                      READ_RESERVED_3, READ_MACHINE_ID, CHECKSUM);
  signal state          : state_type;
  signal next_state     : state_type;
  signal correct_stream : std_logic;
begin  -- synth

  mq : process (correct_stream, state)

  begin  -- process mq
    next_state <= state;
    case state is
      when READ_COP =>
        if correct_stream = '1' then
          next_state <= READ_LONG;
        end if;
      when READ_LONG =>
        if correct_stream = '1' then
          next_state <= READ_RESERVED;
        else
          next_state <= READ_COP;
        end if;
      when READ_RESERVED =>
        if correct_stream = '1' then
          next_state <= READ_RESERVED_2;
        else
          next_state <= READ_COP;
        end if;
      when READ_RESERVED_2 =>
        if correct_stream = '1' then
          next_state <= READ_RECEPTOR;
        else
          next_state <= READ_COP;
        end if;
      when READ_RECEPTOR =>
        if correct_stream = '1' then
          next_state <= READ_RESERVED_3;
        else
          next_state <= READ_COP;
        end if;
      when READ_RESERVED_3 =>
        if correct_stream = '1' then
          next_state <= READ_MACHINE_ID;
        else
          next_state <= READ_COP;
        end if;
      when READ_MACHINE_ID =>
        if correct_stream = '1' then
          next_state <= CHECKSUM;
        else
          next_state <= READ_COP;
        end if;
      when others => null;
    end case;
  end process mq;



  system : process (clk, reset)
  begin  -- process system
    if reset = '0' then                 -- asynchronous reset (active low)

    elsif clk'event and clk = '1' then  -- rising clock edge

    end if;
  end process system;



  process_read_cop : process (byte_entry)
    variable pattern : std_logic_vector(7 downto 0) := "11100100";
    variable valid   : std_logic                    := '1';
  begin
    for i in 0 to 7 loop
      if pattern(i)<>byte_entry(i) then
        valid := '0';
      end if;
    end loop;
    correct_stream <= valid;
  end process process_read_cop;



  process_read_long : process (byte_entry)
    variable pattern : std_logic_vector(7 downto 0) := "00001000";
    variable valid   : std_logic                    := '1';
  begin
    for i in 0 to 7 loop
      if pattern(i)<>byte_entry(i) then
        valid := '0';
      end if;
    end loop;
    correct_stream <= valid;
  end process process_read_long;



  process_read_reserved : process (byte_entry)
    variable valid : std_logic := '1';
  begin
    for i in 0 to 7 loop
      if byte_entry(i)<>'0' then
        valid := '0';
      end if;
    end loop;
    correct_stream <= valid;
  end process process_read_long;



  process_read_receptor : process (byte_entry)
    variable valid : std_logic := '1';
  begin
    for i in 0 to 7 loop
      if byte_entry(i)<>'0' then
        valid := '0';
      end if;
    end loop;
    correct_stream <= valid;
  end process process_read_long;



  process_read_machine_id : process (byte_entry)
    variable valid             : std_logic                    := '1';
    variable pattern_machine_1 : std_logic_vector(7 downto 0) := "00000001";
    variable pattern_machine_2 : std_logic_vector(7 downto 0) := "00000010";
    variable pattern_machine_3 : std_logic_vector(7 downto 0) := "00000011";
  begin
    if (byte_entry & pattern_machine_1) <> pattern_machine_1 then
      if (byte_entry & pattern_machine_2) <> pattern_machine_2 then
        if (byte_entry & pattern_machine_3) <> pattern_machine_3 then
          valid = '0';
        end if;
      end if;
    end if;
    correct_stream <= valid;
  end process process_read_long;


  checksum : process(byte_entry)
    variable chksum : std_logic_vector(7 downto 0) := (others '1');
  begin
    for i in 0 to 7 loop
      
    end loop;  -- i
    
  end process checksum;


  
end synth;  --Fin architecture synth                              


